A common method in the operation of data storage systems is to cache writing data in order to reduce writing latency and improve writing performance. Data storage technology based on NAND Flash memory has continued to develop quickly over the past 10 years. The traditional hard disk drive (HDD) has been replaced in many applications. The main reasons for this include:
High Speed: Data storage in a flash memory is different from that in a traditional HDD, which depends on the mechanical address operation of the magnetic head. Therefore, the speed of reading and writing data is substantially increased, and the strict requirements regarding data storage throughput of applications is met.
Decreasing Price: Due to progress being made in the field of semiconductor technology, flash memory storage capacity has doubled in less than two years, as described by Moore's Law, and the price per storage unit has also decreased. Recently, the price for MLC flash memory has decreased from $10USD/GB, which was the price five years ago, to less than $1USD/GB.
Progress Of The Technology Of The Controller: The flash memory needs a matching controller to communicate with the host for storing, reading, and writing data. The mature development of controller technology has contributed to the solid storage technology based on flash memory so that it can be applied in various areas, which include applications for high-end data centers and mobile smartphones.
The Solid State Disk (SSD) has brought a revolutionary improvement in the performance of data storage systems, and also carries new requests and new opportunities for the writing cache. The system structure of the SSD of the current technology is illustrated in FIG. 1. The host interface is the port of the data read-and-write command. The up-layer application transmits commands of the needed read-and-write data through the host interface. The latency for the flash to write data is about 1 ms, which is quite large, and the latency of mini-second level cannot meet the requirements for the application of key systems. Therefore, a cache module is usually arranged for the design of the controller system. The cache module could be an external DRAM or an internal SRAM in the controller. When data is written to the SSD, the controller reads the writing command and caches the writing data to the cache module. Regarding the traditional SSD design, all data is cached by the cache module, and the writing command is accomplished after the data is written to the cache. Because the writing latency of the cache module is micro-second level, the writing latency could be significantly reduced to improve system performance. During the afterward operations, the controller writes the data in the cache module to the storage medium through the data channel. The storage medium of an SSD is composed of many flash modules. The writing cache system diagram of an SSD is illustrated in FIG. 2.
However, the writing cache method of the current technology has the following problems:
Size Of The Cache: The buffer of liquid data of high bandwidth may need quite a large cache, and it cannot be performed within the controller.
Bandwidth Requirements: If the cache is arranged outside the controller, data will be transmitted from the host to the controller, and from the controller to the cache, and from the cache to the controller, and is finally written to the flash. For the chip of the controller, the bandwidth requirement is four times the user bandwidth.
Data Completeness: It is about how to confirm that the newest data is read accurately. When only a portion of data is written to the flash, it needs to be read from the cache, and it cannot be read from the flash. When the cache is larger, the complexity of determination is larger, and the performance loss is greater.
Data Completeness For Accidental Situation: When power is cut off suddenly, the data in the cache urgently needs to be written to prevent that data from being lost. The larger the cache, the greater the danger of data loss.